A unit comes back with a note that says, in effect, it doesn’t wake up when it’s cold. It boots on the bench at 22°C. It boots in the reflow-adjacent warmth of the factory. It boots in the customer’s office. Then it sits in a vehicle overnight, or on a pole, or in an unheated enclosure, and the first power-on of the morning produces nothing: no boot, no log, no radio. The default diagnosis is the battery, then the firmware, then the power supply. The crystal oscillator gets checked last, usually because someone has to remember it exists.
That ordering is backwards. The oscillator margin measurement is cheap, it takes a scope and a handful of resistors, and the failure class it catches is one of the most common ways a working prototype becomes a product that generates returns. This article separates the three axes that get collapsed into “crystal problem” — negative-resistance margin, drive level, and load capacitance — and lays out a cold-startup bench procedure and a manufacturing test spec that catch the class before it ships.
What this article will not do: it will not claim a specific cold-temperature failure rate, it will not assert that temperature changes crystal ESR or amplifier transconductance by a particular amount (the sources retrieved for this piece don’t quantify that), and it will not pretend the margin guidelines below are a temperature-qualified guarantee. They are design targets to verify, not certificates.
Three axes, not one problem
Failure reports compress everything into “the crystal.” The bench needs to keep three things separate, because a change that fixes one can quietly degrade another.
Negative-resistance margin answers: does the amplifier have enough gain to overcome the crystal’s equivalent series resistance (ESR) and start oscillating? Negative resistance is not a property of the crystal. As TI puts it in its crystal-oscillator application note for the CC13xx/CC26xx/CC23xx/CC27xx families, negative resistance “is a parameter of the complete oscillator circuit, including capacitor values, crystal parameters, and the on-chip circuit” (SWRA495L). You cannot buy margin by buying a better crystal alone; the load caps and the MCU’s drive strength are part of the number.
Drive level answers: how much power is being dissipated in the crystal? TI defines drive level as “the power dissipated in the crystal,” notes that the maximum is usually specified in microwatts on the crystal datasheet, and warns that exceeding it “can damage or reduce the life of the crystal” (SWRA495L). Drive level rarely causes a no-start directly. It causes frequency-temperature drift and long-term aging that show up as returns months later — and Murata lists deviation of the drive level from the standard value as a main factor in abnormal temperature characteristics of oscillation frequency (Murata crystal FAQ).
Load capacitance answers: does the board present the crystal with the CL it was cut for? TI’s oscillator design guide is blunt about the target: the crystal manufacturer’s datasheet specifies the recommended load CL, and the circuit’s load capacitance should equal it (SZZA043). Load capacitance also feeds back into margin: TI’s negative-resistance approximation shows that a low CL gives a larger negative resistance (SWRA495L). So a load-cap change made to fix frequency accuracy can move startup margin in the wrong direction.
What the margin guideline actually says
The commonly cited ratio is a design target, and the two major sources phrase it slightly differently, which matters when you write it into a test spec.
TI recommends that the magnitude of the negative resistance be at least 10 times greater than the ESR during initial startup and at least 5 times greater than the ESR during steady-state operation for automotive applications, and notes that in certain use cases the values can be minimized to at least 3 times during startup — while stating that TI does not recommend operating below these values (SWRA495L).
Murata’s general guideline is 5x or more of the R1 standard value for consumer applications and 10x or more for automotive (Murata crystal FAQ).
Read those together and the practical takeaway is: startup is the harder case than steady state, and the ratio you should be verifying is the startup ratio, measured at the temperature and supply voltage where startup is hardest. If your product is consumer-grade and you design to 5x at room temperature, you have not verified 5x at cold. The guideline is a floor for the measurement, not a substitute for it.
Measuring negative resistance on the bench
The measurement is a destructive-to-the-margin binary search, and TI describes the method directly: introduce a resistor in series with the crystal, use a 0201 package to avoid parasitic effects, and find the threshold where the sum of the extra resistance and the crystal ESR makes the oscillator fail to start. That threshold is approximately the circuit’s negative resistance (SWRA495L).
Procedure, in the order that saves time:
- Measure the crystal’s ESR, or take it from the datasheet at the operating temperature you care about. If the datasheet only gives a room-temperature maximum, treat the cold ESR as unknown and measure the margin at cold directly rather than extrapolating.
- Insert a 0201 resistor in series with the crystal. Start at 0 Ω and confirm the unit starts reliably at the test temperature.
- Step the resistance up until startup fails. Repeat at least ten power cycles at each step; a single successful start is not a pass.
- Record R_fail. Negative resistance magnitude ≈ R_fail. Margin ratio = R_fail / ESR.
- Repeat at the cold corner and at the low-supply corner. The worst combination is the number that goes in the design record.
Two cautions. First, the series resistor changes the circuit you are measuring, so do the drive-level and frequency checks on the unmodified board. Second, the failure threshold is statistical near the edge — a board that starts nine times out of ten at a given resistance is a board that will fail in the field, so treat any intermittent start as a fail.
Measuring drive level
Drive level is computed, not read off a meter. TI gives the relationship in terms of ESR, frequency, load and shunt capacitance, and the peak-to-peak voltage across the crystal pin: DL = 2 × ESR × (πf(CL + C0)Vpp)², where Vpp is the peak-to-peak voltage on the crystal pin (SWRA495L). The measurement you need is Vpp, and the app note’s section on measuring oscillation amplitude describes the probe setup.
Practical notes: use a low-capacitance FET probe (the TCAN455x app note specifies a FET probe with Cin < 1 pF for its frequency measurement setup, and the same discipline applies here — a 10 pF scope probe will load the oscillator and change what you are measuring) (SLLA549). Compute DL at the worst-case Vpp you observe across temperature and supply, and compare it to the datasheet maximum. If you are within 2x of the maximum, you are close enough that lot variation in ESR matters.
There is a second drive-level failure mode that is easy to miss because it looks like a startup problem: over-driving can push the oscillation amplitude high enough that the oscillator’s own detection or bias circuitry misbehaves. TI’s TCAN455x app note describes exactly this: when the total external load is too small, the amplifier’s minimum output current can make the oscillation amplitude too large, and if the OSC2 peak voltage drops below the single-ended clock detection threshold, the amplifier and bias block can be disabled and oscillation stops (SLLA549). That is a device-specific behavior, not a universal rule, but it is a reminder that “more amplitude” is not automatically “more margin.”
The cold-startup test that catches the class
A test that only asks “does it boot at -20°C” will pass units that start slowly, and those units fail in the field when the host MCU’s startup timeout is shorter than the cold start time. The test has to log time-to-start, not just pass/fail.
A workable procedure:
- Soak the unit at the cold corner for long enough that the crystal and board are at temperature, not just the chamber air. Thermocouple on the crystal package, not on the chamber wall.
- Power-cycle. Log the time from enable to first stable clock, using the MCU’s own startup flag if it has one, or a scope trigger on the oscillator output.
- Repeat at least 20 cycles per unit, across at least 5 units from different lots if you have them. Startup is a statistical event near the margin edge.
- Record: did it start, how long did it take, and what was the worst-case time. Compare the worst-case time to the firmware’s startup timeout with margin.
- Repeat at the low-supply corner. Supply voltage and temperature are not independent knobs for the amplifier.
The pass criterion should be written as a time budget, not a boolean. “Starts within X ms at -20°C and minimum supply, 20 of 20 cycles” is a spec a contract manufacturer can test. “Boots cold” is not.
Where margin goes to die at 1k–10k units
At prototype quantities, the crystal and load caps are whatever the design engineer soldered on, from one lot, often hand-selected. At 1k–10k units, four manufacturing decisions move the margin:
Crystal substitution. A second-source crystal with the same nominal frequency and load capacitance can have a different ESR. Since the margin ratio is negative resistance divided by ESR, a higher-ESR substitute eats margin without changing any other visible parameter. The test spec should name the measured margin ratio, not the part number, so a substitution that changes margin is caught at first article.
Load-cap tolerance. The load capacitance the board presents is the series combination of the two load caps plus the pin capacitances plus PCB stray. TI’s TCAN455x app note gives the formula explicitly, including the OSC1 output pin capacitance (typically 10 pF) and OSC2 input pin capacitance (typically 9 pF) for that device, plus PCB stray measured between the crystal footprint pads with the crystal and caps removed (SLLA549). Those pin capacitances are not negligible relative to a 8–12 pF CL, and they are device-specific — copy the formula from your MCU’s app note, not from a different part.
PCB stray capacitance. The same app note’s instruction — measure the parasitic capacitance between the crystal footprint pads with the crystal and load caps not mounted — is the step most often skipped. Stray capacitance varies with layout, and a layout change between prototype and production is a load-capacitance change whether or not anyone touched the caps.
MCU internal capacitor array settings. Many MCUs integrate the load capacitors and let firmware set them. TI’s CC devices, for example, require configuration based on the crystal used, adjusting the internal capacitor array to match the crystal’s load capacitance (SWRA495L). If that setting is calibrated at room temperature on one board and copied into the production image, the cold margin is unverified. Treat the calibration as a per-design measurement with a cold check, not a firmware constant.
Reading the return signature
The three axes produce distinguishable field signatures, which is useful when you are triaging a return batch and deciding which bench measurement to run first.
- No-boot at cold, boots warm, no frequency complaint: startup margin. Run the series-resistor measurement at cold first.
- Intermittent startup at any temperature, worse at cold: margin again, but check the load-cap value against the crystal’s CL before assuming the crystal is at fault. Murata lists mismatch between circuit conditions and crystal specifications alongside insufficient margin as a main cause of no-oscillation (Murata crystal FAQ).
- Boots, but frequency drifts with temperature or ages over months: drive level or load-cap mismatch. Murata lists drive-level deviation as a main factor in abnormal frequency-temperature characteristics (Murata crystal FAQ).
- Small amplitude, unstable operation: Murata lists a limiting resistance that is too large and an inappropriate load capacitance as main factors for insufficient oscillation amplitude (Murata crystal FAQ).
None of these signatures is conclusive on its own. The point is to order the bench work so the cheap measurement runs before the expensive one.
What goes in the contract-manufacturer test spec
The spec should be written so that a substitution or a process change that eats margin fails at first article, not at the customer. A minimum set:
- Negative-resistance margin ratio at the cold corner and low-supply corner, measured by the series-resistor method, with a pass threshold stated as a ratio (e.g., ≥5x startup for consumer, ≥10x for automotive, per the guidelines above).
- Time-to-start at cold, 20 of 20 cycles, with a stated maximum in milliseconds tied to the firmware timeout.
- Drive level computed from measured Vpp, compared to the crystal datasheet maximum, at the worst-case temperature and supply.
- Load capacitance verification: measured PCB stray plus pin capacitances plus cap tolerances, compared to the crystal’s specified CL.
- Change trigger: any crystal part number change, any load-cap value or dielectric change, any PCB layout change near the oscillator, or any MCU internal cap array setting change requires re-running all four measurements at first article.
The last item is the one that matters most at 1k–10k volumes. The most likely margin-eating event at that scale is not a design error — it is a substitution to an “equivalent” part that is equivalent in frequency and package but not in ESR, or a load-cap reel that is the right value in the wrong dielectric. A spec that names the measured margin catches both. A spec that names the part number catches neither.
FAQ
Does cold temperature reduce negative resistance margin? The retrieved sources do not quantify temperature dependence of crystal ESR or amplifier transconductance, so this article does not assert a mechanism. What the sources do support is that startup margin is a property of the complete circuit and that the margin guideline is a design target to verify, not a guarantee at any temperature. The practical response is to measure margin at the cold corner rather than reason about it.
Is 5x enough, or do I need 10x? Murata’s guideline is 5x or more of R1 for consumer and 10x or more for automotive (Murata crystal FAQ). TI recommends 10x at startup and 5x at steady state for automotive, with 3x at startup as a floor it does not recommend going below (SWRA495L). The ratio is a starting point; the measured cold-corner number is the one that goes in the design record.
Can I fix a cold-start problem by lowering the load capacitance? Lower CL does increase the negative-resistance magnitude per TI’s approximation (SWRA495L), but it also pulls the frequency away from the crystal’s specified CL, which is a separate failure. Change load capacitance only as a deliberate trade with the frequency error measured and accepted.
Why does the unit start on the bench but not in the field? The bench is one temperature, one supply, and usually one board. The field is the cold corner, the low-supply corner, and a production lot. The margin measurement exists to close that gap before shipping.
What if my MCU has internal load capacitors? Then the internal capacitor array setting is part of the load capacitance and part of the margin. TI’s CC devices require configuring the internal array to match the crystal’s load capacitance (SWRA495L), and that configuration should be verified at cold, not just at the calibration bench.
